The Cray X1 is a vector supercomputer that Cray Inc. manufactured and sold from 2003. It uses a non-uniform memory access design and is often described as a merger of the earlier Cray T90, Cray SV1 and Cray T3E architectures: it takes the multistreaming processors, vector caches and CMOS construction of the SV1, the scalable distributed memory of the T3E and the memory bandwidth and liquid cooling of the T90. Each processor ran on a 1.2 nanosecond clock cycle and reached a peak of 12.8 gigaflops. Air-cooled models held up to 64 processors, while liquid-cooled systems could in theory grow to 4,096 processors in 1,024 shared-memory nodes joined by a two-dimensional torus network. The largest unclassified installation had 512 processors at Oak Ridge National Laboratory. The machine ran UNICOS/mp and could be programmed with MPI, PVM, Unified Parallel C or Co-array Fortran. Cray released the dual-core X1E upgrade in 2005 and production of both ended in 2007. Development was partly funded by the United States National Security Agency under the code name SV2, and the X1 was not a financial success.
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Source Cray X1 (Wikipedia)
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Source Steven L. Scott (IEEE Computer Society profile)
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Source Cray X1 (Wikipedia)LeadQuote, Lead
manufactured and sold by Cray Inc. since 2003
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1. Cray X1 (Wikipedia)
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manufactured and sold by Cray Inc. since 2003
Lead [status]
production transitioned from X1 to X1E machines, then ended in 2007
In Group: Cray Research and Control Data Vector Supercomputers, Lead [in-group]
non-uniform memory access, vector processor supercomputer manufactured and sold by Cray Inc.
In Field: Computer Architecture, Lead [in-group]
non-uniform memory access, vector processor supercomputer manufactured and sold by Cray Inc.
View the SourceSteven L. Scott (IEEE Computer Society profile)
Invented: Steve Scott (computer architect), Profile textQuote, Invented: Steve Scott (computer architect), Profile text
Scott was the chief architect of the Cray X1/X1E supercomputers
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