Elmore delay

Elmore delay is a simple approximation to the delay through an RC network in an electronic system. It is often used in logic synthesis, delay calculation, static timing analysis, placement and routing because it is easy to compute, especially in tree structured networks, which make up the vast majority of signal nets inside integrated circuits, and because it is reasonably accurate. Even where it is not accurate it is usually faithful, meaning that reducing the Elmore delay almost always reduces the true delay, so it remains useful in optimization. For a tree network the delay is found by taking each segment as its resistance times the downstream capacitance and summing from the root to the sink; for a series RC ladder the delay is the sum over each capacitor of the total resistance leading to it times that capacitance, and the 50 percent propagation delay is the natural logarithm of 2 times that value. The same quantity can be seen as matching one moment of the response, or as a first-order Pade approximation. A branching network is handled by lumping the capacitance of off-path branches at the branch point. Inserting buffers along long wires and tapering wire width are the usual ways to reduce it, each with routing costs the source describes.