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Programming Language

VHDL

Simulation Language

VHDL (VHSIC Hardware Description Language) is a hardware description language used to model and simulate electronic systems, developed in the 1980s by the United States Department of Defense as part of the Very High Speed Integrated Circuits program, and later standardized by the IEEE as IEEE 1076. Like Verilog, VHDL is used to describe the behavior and structure of digital circuits for simulation and synthesis, but derives its syntax from the Ada programming language.

Facts
First Released
1983 2
Paradigm
concurrent, reactive, dataflow 2
Significance
VHDL can model the behavior and structure of digital systems at multiple levels of abstraction, from the system level down to logic gates, and is used for design entry, documentation and verification. 2
Classification
Typing Discipline
Strongly Typed 1
VHDL
Filter Results1 entry
Connections

Influenced

Source Wikidata: SystemVerilog

Influenced By

Ada, Programming Languages

"VHDL borrows heavily from the Ada programming language in both concept and syntax," per the Department of Defense requirement to base VHDL syntax on Ada. en.wikipedia.org/wiki/VHDL

Sources
1. Wikidata: VHDL
  • Wikidata Q209455, resolved via en.wikipedia pageprops (wave rule R-L)
  • Wikidata Q209455 P7078 (typing discipline)
View the Source
2. VHDL - Wikipedia
  • History section, sentence 1
    In 1983, VHDL was originally developed at the behest of the U.S. Department of Defense in order to document the behavior of the ASIC that supplier companies were including in equipment.
  • Infobox, Paradigm
    Paradigm: concurrent, reactive, dataflow
  • Lead paragraph, sentence 1
    VHDL (VHSIC hardware description language) is a hardware description language that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates.
View the Source
Wikidata: SystemVerilog
Influenced: SystemVerilogView the Source
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