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Programming Language

Verilog

Simulation Language

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model and simulate electronic systems, most commonly digital circuits, and to synthesize such designs into physical hardware. Verilog is used in the design, verification and implementation of analog, digital and mixed-signal circuits at varying levels of abstraction, and it was originally developed by Prabhu Goel, Phil Moorby and Chi-Lai Huang at Gateway Design Automation in 1984.

Facts
First Released
1984 2
Paradigm
Structured 2
Significance
At its 1984 introduction, Verilog was a major productivity improvement over the graphical schematic capture tools circuit designers used at the time. 2
Classification
Typing Discipline
Statically Typed 1
Typing Discipline
Weakly Typed 1
FAQs

Is Verilog only used for digital circuits?

It also covers analog and mixed-signal circuits.

No. Verilog is most commonly used for the design and verification of digital circuits, but it is also used to verify analog and mixed-signal circuits, and even in the design of genetic circuits.
Connections

Base Language For

Direction correction: SystemVerilog (IEEE 1800) extends Verilog (IEEE 1364), not the reverse.

Follows Typing Discipline

Weak Typing, Concepts

In Field

Source Verilog - Wikipedia

Influenced

Source Wikidata: SystemVerilog

Invented By

Source Programming Language Database (PLDB): Verilog
Sources
1. Wikidata: Verilog
  • Wikidata Q827773, resolved via en.wikipedia pageprops (wave rule R-L)
  • Wikidata Q827773 P7078 (typing discipline)
View the Source
2. Verilog - Wikipedia
  • Infobox: released
    1984
  • Infobox: paradigm
    Structured
  • Overview section, paragraph 2
    At the time of Verilog's introduction (1984), Verilog represented a tremendous productivity improvement for circuit designers who were already using graphical schematic capture software and specially written software programs to document and simulate electronic circuits.
  • In Field: Computer Architecture, Lead sentence
    Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems.
  • In Group: Hardware Description Languages, Lead
    Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems.
View the Source
Wikidata: SystemVerilog
Influenced: SystemVerilogView the Source
Programming Language Database (PLDB): Verilog
Programming Language Database (PLDB)Invented By: Philip Moorby, Page lead
Quote, Invented By: Philip Moorby, Page lead
created in 1984 by Phil Moorby and Prabhu Goel
View the Source
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