Manolis G.H. Katevenis is Professor Emeritus in the Department of Computer Science at the University of Crete and the founder and honorary head of the Computer Architecture and VLSI Systems laboratory at the Institute of Computer Science of the Foundation for Research and Technology Hellas in Heraklion, Crete. His areas of interest are computer architecture, interprocessor communication, interconnection network architecture and VLSI systems. His 1984 dissertation on reduced instruction set computer architectures for VLSI received the ACM Doctoral Dissertation Award, and he is a member of Academia Europaea. His research page lists work on weighted round robin scheduling and on packet switch architecture, including the ATLAS I single-chip ATM switch.
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Credited
Source Weighted round robin (Wikipedia)
In Field
Source Manolis Katevenis home page (FORTH-ICS)
Invented By
Source Weighted round robin (Wikipedia)
Sources
Manolis Katevenis home page (FORTH-ICS)
In Field: Computer Architecture, LeadQuote, In Field: Computer Architecture, Lead
Computer Architecture and VLSI Systems (CARV) Laboratory,
View the Source Weighted round robin (Wikipedia)
Invented By: Weighted round robin, History
WRR for network packet scheduling was first proposed by Katevenis, Sidiropoulos and Courcoubetis in 1991
Credited: Weighted round robin, History
WRR for network packet scheduling was first proposed by Katevenis, Sidiropoulos and Courcoubetis in 1991
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